Yep you got it. dual core meens 2 CPU's on one chip.
from wiki
DDR:
DDR SDRAM or double-data-rate synchronous dynamic random access memory is a type of memory integrated circuit used in computers. It achieves greater bandwidth than ordinary SDRAM by transferring data on both the rising and falling edges of the clock signal (double pumped). This effectively nearly doubles the transfer rate without increasing the frequency of the front side bus. Thus a 100 MHz DDR system has an effective clock rate of 200 MHz when compared to equivalent SDR SDRAM, the “SDR” being a retrospective designation.
With data being transferred 8 bytes at a time DDR RAM gives a transfer rate of (memory bus clock rate) × 2 (for dual rate) × 8 (number of bytes transferred). Thus with a bus frequency of 100 MHz, DDR-SDRAM gives a max transfer rate of 1600 MB/s.
JEDEC has set standards for speeds of DDR SDRAM, divided into two parts: The first specification is for memory chips and the second is for memory modules.
DDR is slowly being replaced by DDR-2, which has some modifications to allow higher clock frequency, but operates on the same principle as DDR. Competing with DDR-2 will be Rambus XDR-DRAM. It is expected that DDR-2 will become the standard, since QDR (Quad Data Rate) is too complex to implement, while XDR is lacking support.
DDR Prefetch buffer width is 2 bit, DDR-2 uses 4 bit.
Memory manufacturers have stated that it is impractical to mass-produce DDR-1 memory with effective clock rates in excess of 400 MHz. DDR-2 picks up where DDR-1 leaves off, and is available at clock rates of 400 MHz and higher.
RDRAM is an alternative to DDR SDRAM, but most manufacturers have dropped support from their chipsets.
DDR2:
The advantage of DDR2 over DDR SDRAM is the ability for much higher clock speeds, due to design improvements. With a clock frequency of 100 MHz, "SDR-SDRAM" will transfer data on every rising edge of the clock pulse, thus achieving an effective 100 MHz data transfer rate. Unlike SDR, both DDR and DDR2 are double pumped; they transfer data on the rising and falling edge of the clock, at points of 0.0 V and 2.5 V (1.8 V for DDR2), achieving an effective rate of 200 MHz (and a theoretical bandwidth of 1.6 GBps) with the same clock frequency. DDR2's clock frequency is further boosted by electrical interface improvements, on-die termination, prefetch buffers and off-chip drivers. However, latency is greatly increased as a trade-off. DDR2 Prefetch buffer is 4 bits wide, whereas DDR is 2 bits wide & DDR3 is 8 bits wide.
Power savings are achieved primarily due to an improved manufacture process, resulting in a drop in operating voltage (1.8 V compared to DDR's 2.5 V). The lower memory clock frequency could also help — DDR2 can use a real clock frequency 1/2 that of SDRAM whilst maintaining the same bandwidth).
DDR2 was introduced at two initial speeds- 200 MHz (referred to as PC2-3200) and 266 MHz (PC2-4200). Both perform worse than their DDR equivalents since heightened latency makes total access times twice as long in the worst case scenario. However, DDR won't officially be introduced at any speeds above 266 MHz (533 MHz effective). DDR-533, and even DDR-600 SDRAM exists, but JEDEC has stated that they won't be standardized. These modules are mostly manufacturer optimizations of highest-yielding chips, drawing significantly more power than slower-clocked modules, and usually don't offer much, if any, higher real-world performance.
Currently, at least Intel supports DDR2 in their 9xx chipsets. AMD also has plans to add DDR2 support into their AMD64 processors (all of which have on-die memory controllers) during 2006.
DDR2 SDRAM DIMMs have 240 pins (as opposed to 184 pins on DDR DIMMs, and 168 pins on SDRAM DIMMs).
DDR3:
DDR III, likely to be called DDR III SDRAM (Double Data Rate Three Synchronous Dynamic Random Access Memory), is the name of the new DDR memory standard that is being developed as the successor to DDR2 SDRAM.
The memory comes with a promise of a power consumption reduction of 40% compared to current commercial DDR2 modules, due to DDR III's 90 nanometer fabrication technology, allowing for lower operating currents and voltages (1.5V, compared to DDR2's 1.8V or DDR's 2.5V). "Dual-gate" transistors will be used to reduce leakage current.
DDR3 Prefetch Buffer width is 8 bit, whereas DDR2 is 4 bit, and DDR is 2 bit.
Theoretically, these modules could transfer data at the effective clockrate of 400-800 MHz (for a bandwidth of 800-1600 Mb/s), compared to DDR2's current range of 200-533 MHz (400-1066 Mb/s) or DDR's range of 100-300 MHz (200-600 Mb/s). To date, such bandwidth requirements have been mainly on the graphics market, where vast transfer of information between framebuffers is required.
Prototypes were announced in early 2005, while DDR3 specification is expected to be publicly available in mid 2006. Supposedly, Intel has preliminarily announced that they expect to be able to offer support for it near the end of 2007. AMD's roadmap indicates their own adoption of DDR3 to come in 2008.
The GDDR3 memory, with a familiar name but an entirely dissimilar technology, has been in use for several years in high-end graphic cards such as ones from NVIDIA or ATI, and as main system memory on the Xbox 360. It is sometimes incorrectly referred to as "DDR3".
XDR:
XDR DRAM is a high performance RAM Interface like SDR-SDRAM and DDR-SDRAM. The XDR solution was engineered to be effective in small high-bandwidth consumer systems as well as in high-performance main memory applications. Rambus owns the technology. XDR is the official choice by Sony for the PlayStation 3 console.
rambus:
The first PC motherboards with support for RDRAM debuted in 1999. They supported PC800 RDRAM, which operated at 800 MHz and delivered 1600 MB/s of bandwidth over a 16 bit bus using a 184 pin RIMM form factor. This was significantly faster than the previous standard, PC133 SDRAM, which operated at 133 Mhz and delivered 1066 MB/s of bandwidth over a 64 bit bus using a 168 pin DIMM form factor.
Some downsides of RDRAM technology, however, included significantly increased latency, heat output, manufacturing complexity, and cost. PC800 RDRAM operated with a latency of 45ns, compared to only 7.5ns for PC133 SDRAM. RDRAM memory chips also put out significantly more heat than SDRAM chips, necessitating heatsinks on all RIMM devices. RDRAM also includes a memory controller on each memory chip, significantly increasing manufacturing complexity compared to SDRAM, which used a single memory controller located on the northbridge chipset. RDRAM was also two to three times the price of PC133 SDRAM due to a combination of high manufacturing costs and high license fees. DDR SDRAM, introduced in 2000, operated at an effective clockspeed of 266 MHz and delivered 2100 MB/s over a 64-bit bus using a 184 pin DIMM form factor.
With the introduction of the i850 chipset, Intel added support for dual-channel PC800 RDRAM, doubling bandwidth to 3200 MB/s by increasing the bus width to 32 bit. This was followed in 2002 by the i850E chipset, which introduced PC1066 RDRAM, increasing total dual-channel bandwidth to 4200 MB/s. Also in 2002, Intel released the E7205 Granitebay chipset, which introduced dual-channel DDR support for a total bandwidth of 4200 MB/s, but at a much lower latency than competing RDRAM. In 2003, Intel released the i875P chipset, and along with it dual-channel DDR400. With a total bandwidth of 6400 MB/s, it marked the end of RDRAM as a technology with competitive performance.
Last edited by Morbo; 31/01/06 12:25 PM.
